Semiconductor device

ABSTRACT

A semiconductor device includes multiple electrode pads provided in an interconnection layer over a semiconductor substrate; an insulating layer provided on the interconnection layer so as to expose portions of the electrode pads; multiple conductive layers having their respective first ends connected to the exposed portions of the corresponding electrode pads so as to extend therefrom on the insulating layer; and multiple protruding electrodes provided at respective second ends of the conductive layers, wherein the conductive layers extend in a given direction relative to the electrode pads.

CROSS-REFERENCE TO RELATED APPLICATION

This application is a continuation application filed under 35 U.S.C.111(a) claiming benefit under 35 U.S.C. 120 and 365(c) of PCTInternational Application No. PCT/JP2007/064601, filed on Jul. 25, 2007,the entire contents of which are incorporated herein by reference.

FIELD

A certain aspect of the embodiments discussed herein is related to asemiconductor device.

BACKGROUND

In these years, as electronic apparatuses have become more sophisticatedand faster in operating speed, semiconductor devices to be mounted onsuch electronic apparatuses also have been desired to be moresophisticated, more integrated, and smaller in size. Therefore,so-called flip chip mounting has been employed as a method for mountinga semiconductor device (element) on a support board such as a wiringboard, by which the semiconductor device is mounted face-down on thewiring board through external connection protruding electrodes calledsolder bumps.

FIG. 1 illustrates a surface having solder bumps provided thereon ofsuch a semiconductor device (element) to which flip chip mounting isapplied. FIG. 2 illustrates a cross section of the semiconductor deviceof FIG. 1 taken along broken line A-A.

Referring to FIG. 1 and FIG. 2, in a semiconductor device (element) 30,multiple functional elements (not graphically illustrated) includingactive elements such as a transistor and passive elements such as acapacitive element are formed on one of the principal surfaces of asemiconductor substrate 1 of silicon (Si) through application of aso-called wafer process. These functional elements including activeelements and passive elements are interconnected through a multi-layerinterconnection layer 3, formed over the principal surface of thesemiconductor substrate 1 with interposition of an insulating layer 2such as a silicon oxide (SiO₂) layer, so that an electronic circuit isformed.

This multi-layer interconnection layer 3 includes multipleinterconnection layers 4 and multiple interlayer insulating layers 5.The interconnection layers 4 are formed of a material such as aluminum(Al) or copper (Cu), and are stacked alternately with two or more of theinterlayer insulating layers 5. The functional elements formed betweenthe upper and lower interconnection layers 4 and in the semiconductorsubstrate 1 are suitably connected through interlayer connection parts6.

A low dielectric constant material (a so-called low-k material) such asorganic resin, silicon oxycarbide (SiOC), or fluorine (F) doped siliconglass (FSG) is used as the material of the interlayer insulating layers5 so as to reduce the capacitance between interconnects and increase therate of electrical signal transmission.

Multiple aluminum (Al) electrode pads 7 are selectively provided at thetop of the multi-layer interconnection layer 3, and are suitablyconnected to the interconnection layers 4 of the multi-layerinterconnection layer 3.

An inorganic insulating layer 8, which is formed of, for example,silicon nitride (SiN) or silicon oxide (SiO₂) and also referred to as apassivation layer, is selectively provided on the multi-layerinterconnection layer 3. The inorganic insulating layer 8 selectivelyincludes openings so as to expose the center parts of the electrode pads7.

Further, in order to protect the surface of the semiconductor device 30,an organic insulating layer 9 is selectively provided so as to cover theupper surface of the inorganic insulating layer 8 and the end faces ofthe inorganic insulating layer 8 on the electrode pads 7.

The material of the organic insulating layer 9 is selected from organicinsulating materials such as polyimide, benzocyclobutene, phenolicresin, and polybenzoxazole.

A first under-bump metallization (UBM) layer 10 of titanium (Ti) orchromium (Cr) and a second UBM layer 11 of nickel (Ni) or copper (Cu)are stacked on the portions of the electrode pads 7 which portions arenot covered with the inorganic insulating layer 8 or the organicinsulating layer 9. The first UBM layer 10 and the second UBM layer 11are provided in the openings of the organic insulating layer 9 so as tocover its end faces and their periphery.

Substantially spherical external connection protruding electrodes 12 areprovided on the second UBM layer 11. The external connection protrudingelectrodes 12 are formed of lead-free (Pb-free) solder such astin-silver (Sn—Ag) solder or tin-silver-copper (Sn—Ag—Cu) solder, andare also referred to as solder bumps.

The semiconductor device 30 having the above-described structure isformed through the following process.

That is, the inorganic insulating layer 8 and the organic insulatinglayer 9 are provided on the multi-layer interconnection layer 3 so as toselectively expose the electrode pads 7 selectively provided at the topof the multi-layer interconnection layer 3. The inorganic insulatinglayer 8 and the organic insulating layer 9 are deposited by so-calledvapor deposition. So-called photoetching may be applied to the selectiveformation of openings in the inorganic insulating layer 8 and theorganic insulating layer 9.

Next, the first UBM layer 10 is formed so as to extend on the organicinsulating layer 9 and the exposed portions of the electrode pads 7. Thefirst UBM layer 10 may be deposited by so-called sputtering.

Next, a photoresist layer is formed on the first UBM layer 10. Thephotoresist layer is exposed to light, developed, and hardened so as toform openings in the photoresist layer, which openings correspond towhere the external connection protruding electrodes 12 are to be formedover the corresponding electrode pads 7.

Next, electroplating is performed to form the second UBM layer 11 on thefirst UBM layer 10 exposed in the openings in the photoresist layer.Then, an external connection electrode layer is formed on the second UBMlayer 11. At this point, the external connection electrode layer isformed to extend on the photoresist layer.

Thereafter, the photoresist layer is removed. Further, unnecessaryportions of the first UBM layer 10 are removed using the externalconnection electrode layer as an etching mask.

Next, the external connection electrode layer is caused to melt byreflow heating so as to be shaped into substantial spheres. As a result,the semiconductor device 30 is formed, where the substantially sphericalexternal connection protruding electrodes 12 are formed on the secondUBM layer 11 over the semiconductor substrate 1.

FIG. 3 illustrates the semiconductor device 30 flip-chip mounted on awiring board 21. The semiconductor device 30 is mounted face-down on thewiring board 21. The wiring board 21 is formed of an organic built-upsubstrate formed of a glass epoxy material or a polyimide tape. Multipleelectrode pads 22 are selectively provided on a first principal surface(upper surface) of the wiring board 21, which surface is covered withsolder resist 23. The solder resist 23 selectively has openings so as toexpose the center parts of the electrode pads 22.

The external connection protruding electrodes 12 of the semiconductordevice 30 are connected to the corresponding electrode pads 22 providedon the wiring board 21. Further, the space between the semiconductordevice 30 and the wiring board 21 is filled with a so-called underfillmaterial 24. Multiple external connection protruding electrodes 25formed of solder are provided on a second principal surface (lowersurface) of the wiring board 21.

A semiconductor device 50 having the above-described structure is formedthrough the following process.

That is, the semiconductor device 30 is flip-chip mounted (mountedface-down) on the first principal surface (upper surface) of the wiringboard 21.

Next, the external connection protruding electrodes 12 of thesemiconductor device 30 and additional solder (a solder precoat) (notgraphically illustrated) provided in advance on the electrode pads 22 ofthe wiring board 21 are caused to melt by reflow heating, so that theexternal connection protruding electrodes 12 of the semiconductor device30 are connected (joined) to the corresponding electrode pads 22 on thewiring board 21.

Next, the space between the semiconductor device 30 and the wiring bard21 is filled with the underfill material 24, and the underfill material24 is then hardened.

Thereafter, solder balls are provided on the second principal surface(lower surface) of the wiring board 21 so as to form the externalconnection protruding electrodes 25 through a reflow heating process anda cooling process.

Thus, in order to prevent degradation of the electrical characteristicsof a semiconductor device at the time of providing external connectionterminals on a semiconductor substrate, a semiconductor device has beenproposed that includes an internal interconnection layer connected to anelectronic circuit formed in a semiconductor substrate; a via connectedto the internal interconnection layer at any position on thesemiconductor substrate and exposed on the surface of a protection layerformed on the semiconductor substrate; an interconnection layer formedon the protection layer and connected to the via; and an externalconnection terminal connected to the interconnection layer and having apredetermined height, wherein no electronic circuit is providedimmediately below the via, and the diameter of the via is less than orequal to the width of the interconnection layer. (See, for example,Japanese Laid-open Patent Publication No. 2000-243876.)

Further, a semiconductor integrated circuit device has been proposedwhere a solder bump electrode containing tin (Sn) is provided on anunder-bump conductor layer on an extension electrode of a semiconductorintegrated circuit formed on a semiconductor substrate and theunder-bump conductor layer is formed by providing a conductor layercontaining palladium (Pd) on a conductor layer with an adhesion functionprovided on the extension electrode. (See, for example, Japanese PatentNo. 3645391.)

SUMMARY

According to an aspect of the invention, a semiconductor device includesa plurality of electrode pads provided in an interconnection layer overa semiconductor substrate; an insulating layer provided on theinterconnection layer so as to expose portions of the electrode pads; aplurality of conductive layers having respective first ends thereofconnected to the exposed portions of the corresponding electrode pads soas to extend therefrom on the insulating layer; and a plurality ofprotruding electrodes provided at respective second ends of theconductive layers, wherein the conductive layers extend in a givendirection relative to the electrode pads.

The object and advantages of the invention will be realized and attainedby means of the elements and combinations particularly pointed out inthe claims.

It is to be understood that both the foregoing general description andthe following detailed description are exemplary and explanatory and notrestrictive of the invention, as claimed.

BRIEF DESCRIPTION OF THE DRAWING(S)

FIG. 1 is a plan view of a conventional semiconductor device (element)illustrating its structure;

FIG. 2 is a cross-sectional view of the semiconductor device of FIG. 1taken along line A-A;

FIG. 3 is a diagram illustrating the semiconductor device of FIG. 1 andFIG. 2 flip-chip mounted on a wiring board;

FIG. 4 is a plan view of a semiconductor device (element) applied to asemiconductor device according to a first embodiment;

FIG. 5A is a cross-sectional view of the semiconductor device (element)of FIG. 4 taken along broken line A-A according to the first embodiment;

FIG. 5B is an enlarged view of a circled portion of FIG. 5A according tothe first embodiment;

FIG. 6 is a diagram illustrating a variation of the semiconductor device(element) illustrated in FIGS. 5A and 5B according to the firstembodiment;

FIG. 7 is a diagram illustrating the semiconductor device of FIG. 4 andFIGS. 5A and 5B flip-chip mounted on a wiring board according to thefirst embodiment;

FIG. 8 is a plan view of a first variation of the form of the leadingout and extension of the layered structure of a first under-bumpmetallization (UBM) layer and a second UBM layer in the semiconductordevice (element) according to the first embodiment;

FIG. 9 is a plan view of a second variation of the form of the leadingout and extension of the layered structure of a first under-bumpmetallization (UBM) layer and a second UBM layer in the semiconductordevice (element) according to the first embodiment;

FIGS. 10A and 10B are diagrams illustrating a structure of asemiconductor device (element) applied to a semiconductor deviceaccording to a second embodiment; and

FIG. 11 is a flowchart for illustrating a method of manufacturing asemiconductor device according to the first embodiment.

DESCRIPTION OF EMBODIMENTS

As described above, according to the method of manufacturing asemiconductor device where the semiconductor device (element) 30 isflip-chip mounted on the wiring board 21 through the external connectionprotruding electrodes 12 provided on the surface of the semiconductordevice 30, the external connection protruding electrodes 12 of thesemiconductor device 30 and the electrode pads 22 on the wiring board 21are connected by causing the external connection protruding electrodes12 and the coating of additional solder (solder precoat) provided inadvance on the electrode pads 22 of the wiring board 21 to melt in areflow heating process. Thereafter, cooling is performed to solidify theexternal connection protruding electrodes 12.

The silicon (Si) substrate 1 of this semiconductor device 30 has acoefficient of thermal expansion of approximately 3 ppm/° C. toapproximately 4 ppm/° C., while the wiring board 21 formed of an organicmaterial has a coefficient of thermal expansion of approximately 10ppm/° C. to approximately 17 ppm/° C. Thus, the wiring board 21 has acoefficient of thermal expansion greater than that of the semiconductordevice 30.

Accordingly, cooling after the reflow heating process for heating theexternal connection protruding electrodes 12 generates a conspicuousstrain or stress based on the difference between the coefficient ofthermal expansion of the semiconductor device 30 and the coefficient ofthermal expansion of the wiring board 21. That is, since the wiringboard 21 has a coefficient of thermal expansion greater than that of thesemiconductor device 30, such cooling causes stress to be exerted ontothe semiconductor device 30 from the wiring board 21, which expands orcontracts to a greater extent in response to a change in temperature.

This state occurs when the solder material (the external connectionprotruding electrodes 12 and additional solder) is solidified.Accordingly, the stress exerted onto the semiconductor device from thewiring board 21 is not absorbed by the solder (material).

Accordingly, the stress exerted from the wiring board 21 onto theexternal connection protruding electrodes 12 of the semiconductor device30 is exerted onto the interlayer insulating layers 5 formed of aso-called low-k material in the multi-layer interconnection layer 3through the second UBM layer 11, the first UBM layer 10, and theelectrode pads 7.

As a result, interlayer separation occurs in the interconnection layers4 stacked alternately with two or more of the interlayer insulatinglayers 5, thus causing electrical failure in the semiconductor device50.

According to an aspect of the present invention, a semiconductor deviceis provided that, at the time of mounting a semiconductor element on awiring board through the external connection protruding electrodes ofthe semiconductor element, may relieve stress exerted from the wiringboard through the external connection protruding electrodes onto themulti-layer interconnection part of the semiconductor element includinginterlayer insulating layers formed of a low-k material, therebypreventing occurrence of interlayer separation in the interconnectionlayers.

Preferred embodiments of the present invention will be explained withreference to accompanying drawings.

First Embodiment

FIG. 4 illustrates a principal surface of a semiconductor device(element) according to a first embodiment. FIG. 5A illustrates a crosssection of the semiconductor device of FIG. 4 taken along broken lineA-A. FIG. 5B is an enlarged view of a circled portion 500 of FIG. 5A.

Referring to FIG. 4 and FIGS. 5A and 5B, in a semiconductor device(element) 100 according to the first embodiment, multiple functionalelements (not graphically illustrated) including active elements such asa transistor and passive elements such as a capacitive element areprovided on one of the principal surfaces of a semiconductor substrate41 of silicon (Si) through application of a so-called wafer process.

These functional elements including active elements and passive elementsare interconnected through a multi-layer interconnection layer 43,formed over the principal surface of the semiconductor substrate 41 withinterposition of an insulating layer 42 such as a silicon oxide (SiO₂)layer, so that an electronic circuit is formed.

According to this configuration, as illustrated in FIG. 5A, themulti-layer interconnection layer 43 includes multiple interconnectionlayers 44 and multiple interlayer insulating layers 45. Theinterconnection layers 44 are formed of a material such as aluminum (Al)or copper (Cu), and are stacked alternately with two or more of theinterlayer insulating layers 45. The functional elements formed betweenthe upper and lower interconnection layers 44 and in the semiconductorsubstrate 41 are suitably connected through interlayer connection parts46. That is, part of the interconnection layers 44 selectivelypenetrates through the insulating layer 42 to be connected to thefunctional elements formed in the semiconductor substrate 41.

The interlayer connection parts 46 are formed of a material such asaluminum (Al), copper (Cu), or tungsten (W).

A material having a relative dielectric constant lower than or equal to5 (a so-called low-k material) such as organic resin, silicon oxycarbide(SiOC), or fluorine (F) doped silicon glass (FSG) is used as thematerial of the interlayer insulating layers 45 so as to reduce thecapacitance between interconnects and increase the rate of electricalsignal transmission.

Multiple aluminum (Al) electrode pads (electrode parts) 47 are providedat the top of the multi-layer interconnection layer 43, and are suitablyconnected to the interconnection layers 44 of the multi-layerinterconnection layer 43. Referring to FIG. 4, the electrode pads 47 areprovided in a grid-like manner, that is, at substantially equalintervals vertically and horizontally, like a so-called matrix on aprincipal surface of the semiconductor device 100.

Further, an inorganic insulating layer (film) 48, which is formed of,for example, silicon nitride (SiN) or silicon oxide (SiO₂), isselectively provided on the multi-layer interconnection layer 43 so asto have openings that expose the center parts of the electrode pads 47.The inorganic insulating layer 48 is also referred to as a passivationlayer.

The openings of the inorganic insulating layer 48 on the electrode pads47 are greater than or equal to 15 μm in diameter. Opening diameterssmaller than 15 μm increases contact resistance so as to make itdifficult to establish good electrical connection.

Further, in order to protect the surface of the semiconductor device100, an organic insulating layer (film) 49 is provided so as to coverthe upper surface of the inorganic insulating layer 48 and the end faces(internal side faces) of the inorganic insulating layer 48 on theelectrode pads 47.

An insulating material having a Young's modulus of approximately 2 GPato approximately 20 GPa is applied as the organic insulating layer 49.The insulating material is selected from, for example, polyimide,benzocyclobutene, phenolic resin, and polybenzoxazole. The organicinsulating layer 49 is more than or equal to 5 μm in film thickness.

A first under-bump metallization (UBM) layer 50 and a second UBM layer51 are stacked in layers on the exposed portions of the electrode pads47, that is, the surfaces of the electrode pads 47 that are not coveredwith the inorganic insulating layer 48 or the organic insulating layer49, to extend on the organic insulating layer 49. The layered structuresof the first UBM layer 50 and the second UBM layer 51 gradually increasein width (indicated as W by double-headed arrows in FIG. 4) as theyextend in a direction away from the exposed portions of thecorresponding electrode pads 47.

As illustrated in FIG. 5B, the first UBM layer 50 includes a lowermetallization layer 50A of titanium (Ti) or chromium (Cr) and an uppermetallization layer 50B of copper (Cu) provided on the lowermetallization layer 50A. These lower and upper metallization layers 50Aand 50B are deposited by sputtering. The material of the lowermetallization layer 50A is selected (determined) also in view ofadhesion to the organic insulating material of the organic insulatinglayer 49.

On the other hand, copper (Cu) or nickel (Ni) is applied as the secondUBM layer 51. The metallization layer of the second UBM layer 51 isdeposited by plating. At this point, the upper metallization layer 50Bof the first UBM layer 50 facilitates deposition of the second UBM layer51. The second UBM layer 51 is more than or equal to 5 μm in thickness,and supports relaxation of stress at the time of thermal contraction.

Protruding electrodes for external connection (external connectionprotruding electrodes) 52 are selectively provided on the second UBMlayer 51. The external connection protruding electrodes 52 include anunderlayer 52A formed of nickel (Ni) or copper (Cu) and a low-meltingmetal layer 52B provided on the underlayer 52A.

The low-melting metal layer 52B is formed of an alloy whose meltingpoint is lower than or equal to approximately 350° C., for example,so-called lead-free solder or solder that does not contain lead (Pb),such as tin-silver (Sn—Ag) solder or tin-silver-copper (Sn—Ag—Cu)solder. The low-melting metal layer 52B is also referred to as a solderbump. The area of contact of the low-melting metal layer 52B with theunderlayer 52A is larger than the area of the electrode pad 47.

A metal coating of gold (Au), copper (Cu), nickel (Ni), or tin (Sn) maybe provided or formed on the surfaces of the external connectionprotruding electrodes 52. The shape of the external connectionprotruding electrodes 52 is not limited to a substantial hemisphere asillustrated in FIG. 5A, and may be substantially cylindrical.

According to this configuration, as illustrated in FIG. 4, the layeredstructures of the first UBM layer 50 and the second UBM layer 51connected to the corresponding electrode pads 47 are provided to extendin the same (uniform) direction with the same (uniform) length.

As a result, the external connection protruding electrodes 52 areprovided at substantially equal intervals vertically and horizontallylike a so-called matrix, at substantially the same intervals as theintervals at which the electrode pads 47 are provided, on the principalsurface of the semiconductor device 100.

As illustrated in FIG. 6, the semiconductor device 100 may have aninsulating material part 55 of organic matter covering the upper surfaceof the organic insulating layer 49 and the exposed portions of the uppersurfaces of the layered structures of the first UBM layer 50 and thesecond UBM layer 51, which exposed portions are not covered with theexternal connection protruding electrodes 52.

Such covering with the insulating material part 55 makes it possible toprevent oxidation of the surface of the second UBM layer 51 and toprotect the organic insulating layer 49.

FIG. 7 illustrates a semiconductor device 200 having the semiconductordevice (element) 100 configured as described above flip-chip mounted on(over) a wiring board 71.

The wiring board 71 is formed of an organic built-up substrate formed ofa glass epoxy material or a polyimide tape. Multiple electrode pads 72are selectively provided on a first principal surface (upper surface) ofthe wiring board 71. A solder resist 73 having openings so as to exposethe center parts of the electrode pads 72 is selectively provided on thefirst principal surface of the wiring board 71.

The external connection protruding electrodes 52 of the semiconductordevice 100 are connected to the corresponding electrode pads 72 providedon the wiring board 71. The space between the semiconductor device 100and the wiring board 71 is filled with so-called underfill material 74.Further, multiple external connection protruding electrodes 75 formed ofsolder are provided on a second principal surface (lower surface) of thewiring board 71.

As described above, in the semiconductor device 100 according to thefirst embodiment, the first and second UBM layers 51 and 52 extend fromthe electrode pads 47 so as to have the external connection protrudingelectrodes 52 positioned and provided in regions offset sideward fromthe electrode pads 47. That is, the entire lower surfaces of theexternal connection protruding electrodes 52 are positioned over theorganic insulating layer 49 with interposition of the second UBM layer51 and the first UBM layer 50.

Accordingly, even if cooling after reflow heating at the time ofmounting the semiconductor device 100 on the wiring board 71 causes astress to be exerted onto the external connection protruding electrodes52 of the semiconductor device 100 from the wiring board 71 based on thedifference between the coefficients of thermal expansion of thesemiconductor device 100 and the wiring board 71, the stress isprevented from directly affecting the electrode pads 47. The stress isdispersed (distributed) among the second UBM layer 51, the first UBMlayer 50, and the organic insulating layer 49 to be relieved.

This prevents the stress exerted on the external connection protrudingelectrodes 52 of the semiconductor device 100 from working on theinterlayer insulating layers 45 formed of a so-called low-k material inthe multi-layer interconnection layer 43 through the electrode pads 47at the time of mounting the semiconductor device 100 on the wiring board71. Further, it is possible to prevent occurrence of interlayerseparation in the interconnection layers 44 stacked alternately with twoor more of the interlayer insulating layers 45 and thus to avoidoccurrence of electrical failure in the semiconductor device 200.

The organic insulating layer 49, which has elasticity, contributes todistribution (reduction) of the stress exerted toward the second UBMlayer (second metal part) 51 from the wiring board 71 through theexternal connection protruding electrodes 52 at the time of mounting thesemiconductor device (element) 100 on the wiring board 71.

The direction in which the layered structures of the first UBM layer 50and the second UBM layer 51 are led out and extend in the semiconductordevice 100 is not limited to the one described in this embodiment, andmay be selected from various options. That is, for example, theconfiguration illustrated in FIG. 8 or FIG. 9 may also be employed.

FIG. 8 illustrates a first variation of the form of the leading out andextension of the layered structure of the first UBM layer 50 (notgraphically illustrated in FIG. 8) and the second UBM layer 51 in asemiconductor device (element) 110 according to the first embodiment.

The electrode pads 47 are provided in a grid-like manner, that is, atequal intervals vertically and horizontally, on a principal surface ofthe semiconductor device 110 except its center part. Here, the electrodepads 47 are divided into four groups with respect to their positions atwhich they are provided. The layered structures of the first UBM layer50 and the second UBM layer 51 connected to the corresponding electrodepads 47 are grouped in correspondence to the groups of the electrodepads 47. The four groups of the layered structures are led out to extendtoward the respective four corners (corner parts) of the semiconductordevice 110.

This configuration makes it possible to have more latitude in arrangingthe external connection protruding electrodes 52 without the positionsof the adjacent external connection protruding electrodes 52 overlappingeach other, and to prevent formation of the external connectionprotruding electrodes 52 with directional bias in the vicinity of theend portions of the principal surface of the semiconductor device 110.

FIG. 9 illustrates a second variation of the form of the leading out andextension of the layered structure of the first UBM layer 50 (notgraphically illustrated in FIG. 9) and the second UBM layer 51 in asemiconductor device (element) 120 according to the first embodiment.

The electrode pads 47 are provided in a grid-like manner, that is, atequal intervals vertically and horizontally, on a principal surface ofthe semiconductor device 120 as if to be distributed among the fourcorners (corner parts) of the principal surface.

The electrode pads 47 are divided into four groups with respect to theirpositions at which they are provided. The layered structures of thefirst UBM layer 50 and the second UBM layer 51 connected to thecorresponding electrode pads 47 are grouped in correspondence to thegroups of the electrode pads 47. The four groups of the layeredstructures are led out to extend toward the substantial center of thesemiconductor device 120 (from the electrode pads 47 in a direction awayfrom the respective four corners).

This configuration also makes it possible to have more latitude inarranging the external connection protruding electrodes 52 without thepositions of the adjacent external connection protruding electrodes 52overlapping each other, and to prevent formation of the externalconnection protruding electrodes 52 with directional bias in thevicinity of the end portions of the principal surface of thesemiconductor device 120.

In general, in a wiring board on which a semiconductor device (element)is mounted, a greater stress is exerted on the four corners (cornerparts) of the semiconductor device by expansion or contraction due to achange in temperature. Accordingly, it is possible to suppress or reducethe stress to be exerted on the electrode pads 47 by thus providing thelayered structures of the first UBM layer 50 and the second UBM layer 51and providing the external connection protruding electrodes 52 atpositions offset toward the center of the semiconductor device 120 fromthe positions of the electrode pads 47.

Second Embodiment

Next, a description is given, with reference to FIGS. 10A and 10B, of asemiconductor device (element) according to a second embodiment.

FIGS. 10A and 10B illustrate one of the external connection protrudingelectrodes 52 and an interconnection layer structure connected to theone of the external connection protruding electrodes 52 in asemiconductor device (element) 150 according to the second embodiment.FIG. 10A illustrates the one of the external connection protrudingelectrodes 52 and a cross-sectional view of the interconnection layerstructure connected to the one of the external connection protrudingelectrodes 52. FIG. 10B illustrates a planar shape of an electrode padpart before the one of the external connection protruding electrodes 52and an under-bump metallization (UBM) layer are provided on theelectrode pad part. FIG. 10A corresponds to the cross section of FIG.10B taken along line A-A′.

In FIGS. 10A and 10B, the elements or configurations corresponding tothose of the semiconductor device 100 according to the first embodimentare referred to by the same reference numerals.

In the semiconductor device 150 according to the second embodiment,multiple functional elements (not graphically illustrated) includingactive elements such as a transistor and passive elements such as acapacitive element are provided on one of the principal surfaces of thesemiconductor substrate 41 of silicon (Si) through application of aso-called wafer process. Further, the multi-layer interconnection layer43 is formed over the principal surface of the semiconductor substrate41 with interposition of the insulating layer 42 such as a silicon oxide(SiO₂) layer.

The multi-layer interconnection layer 43 includes the multipleinterconnection layers 44 and the multiple interlayer insulating layers45. The interconnection layers 44 are stacked alternately with two ormore of the interlayer insulating layers 45. The upper and lowerinterconnection layers 44 are suitably connected through the interlayerconnection parts 46.

The multiple aluminum (Al) electrode pads (electrode parts) 47 areprovided at the top of the multi-layer interconnection layer 43, and aresuitably connected to the interconnection layers 44 of the multi-layerinterconnection layer 43. According to this embodiment as well, theelectrode pads 47 are provided in a grid-like manner, that is, atsubstantially equal intervals vertically and horizontally, like aso-called matrix on a principal surface of the semiconductor device 150.

Further, the inorganic insulating layer 48, which is formed of, forexample, silicon nitride (SiN) or silicon oxide (SiO₂) and has openingsthat selectively expose the surfaces of the electrode pads 47, and theorganic insulating layer 49 of polyimide or the like are stacked andprovided on the multi-layer interconnection layer 43.

According to one aspect of this embodiment, the insulating layers 48 and49 are formed selectively on the electrode pads 47 so as to divide thesurfaces of the electrode pads 47 into multiple regions and expose thedivided regions. That is, the inorganic insulating layer 48 thatselectively covers the surfaces of the electrode pads 47 and the organicinsulating layer that covers the upper and side surfaces of theinorganic insulating layer 48 are provided on the electrode pads 47.

As a result, the organic insulating layer 49 covers the surface of theinorganic insulating layer 48 and selectively exposes the surfaces ofthe electrode pads 47.

According to this embodiment, as illustrated in FIG. 10B, the inorganicinsulating layer 48 is provided like a crisscross on the surfaces of theelectrode pads 47, and the organic insulating layer 49 is furtherprovided to cover the inorganic insulating layer 48.

As a result, the surface of each of the electrode pads 47 is dividedinto four regions 47 a, 47 b, 47 c, and 47 d, which are exposed atcorresponding sector-shaped openings 49A in the organic insulatinglayers 49.

The electrode pads 47 are in contact with an under-bump metallization(UBM) layer 57 at each of the sector-shaped openings 49A. That is, theUBM layer 57 is connected to each of the electrode pads 47 at fourdifferent (separate) points.

The UBM layer 57 is less in thickness than the stacked layers of theorganic insulating layer 49 and the inorganic insulating layer 48, andis formed in steps over the outside and the inside of the sector-shapedopenings 49A.

The UBM layer 57 has a three-layer structure of a lower layer formed ofthe same material as the first UBM layer 50 in the first embodiment, anintermediate layer formed of the same material as the second UBM layer51 of the first embodiment, and an upper layer formed of the samematerial as the underlayer 52A (for example, FIG. 5A) of the externalconnection protruding electrodes 52.

The external connection protruding electrodes 52 are provided on the UBMlayer 57. The external connection protruding electrodes 52 areelectrically connected to the corresponding electrode pads 47 throughthe UBM layer 57.

According to this semiconductor device (element) structure, even ifcooling after reflow heating at the time of mounting the semiconductordevice 150 on the wiring board 71 (FIG. 7) causes a stress to be exertedonto the external connection protruding electrodes 52 of thesemiconductor device 150 from the wiring board 71 based on thedifference between the coefficients of thermal expansion of thesemiconductor device 150 and the wiring board 71, the stress exertedonto the external connection protruding electrodes 52 is divided to beapplied to separate regions of the surface of each of the electrode pads47. That is, the stress is applied to each of the electrode pads 47 in adispersive manner. This reduces stress concentration in each electrodepad 47.

Accordingly, in this embodiment as well, it is possible to prevent thestress exerted on the external connection protruding electrodes 52 ofthe semiconductor device 150 from working on the interlayer insulatinglayers 45 formed of a so-called low-k material in the multi-layerinterconnection layer 43 through the electrode pads 47 at the time ofmounting the semiconductor device 150 on the wiring board 71. This makesit possible to prevent occurrence of interlayer separation in theinterconnection layers 44 stacked alternately with two or more of theinterlayer insulating layers 45 and thus to avoid occurrence ofelectrical failure in the semiconductor device 200 (FIG. 7).

According to the example illustrated in FIGS. 10A and 10B, the exposedsurface of each of the electrode pads 47 is divided into foursector-shaped regions. However, this embodiment is not limited to thisconfiguration.

That is, the shape of openings provided in the insulating layer coveringthe surfaces of the electrode pads 47 may be selected or determined asrequired. By providing two or more openings, it is possible todistribute the stress exerted on the external connection protrudingelectrodes 52 of the semiconductor device 150 at the time of mountingthe semiconductor device 150 on the wiring board 71.

Semiconductor Device Manufacturing Method According to First Embodiment

A description is given, with reference to FIGS. 5A and 5B, FIG. 7, FIG.9, and FIG. 11, of a method of manufacturing the semiconductor device200 according to the first embodiment.

First, in step S1 of FIG. 11, the first UBM layer 50 is deposited bysputtering on the organic insulating layer 49 having openings formedselectively to expose the electrode pads 47 provided over one of theprincipal surfaces of the semiconductor substrate 41 with interpositionof the multi-layer interconnection layer 43. At this point, the openingsof the organic insulating layer 40 that expose the electrode pads 47 areset to, for example, 15 μm or more in diameter, and the organicinsulating layer 49 is set to, for example, approximately 5 μm or morein film thickness.

Next, in step S2, a photoresist layer is formed on the first UBM layer50 by spin coating. The photoresist layer is exposed to light,developed, and hardened so as to form openings in the photoresist layerat positions corresponding to where the second UBM layer 51 is to beformed.

The openings are formed at positions offset in the same (uniform)direction from where the electrode pads 47 are formed in the caseillustrated in FIGS. 5A and 5B; at positions offset toward the outeredge of the semiconductor device 110 from where the electrode pads 47are formed in the case illustrated in FIG. 8; and at positions offsettoward the center of the semiconductor device 120 from where theelectrode pads 47 are formed in the case illustrated in FIG. 9.

Next, in step S3, the second UBM layer 51 is formed in the openings ofthe photoresist layer by electroplating. At this point, the thickness ofthe second UBM layer 51 is set to, for example, 5 μm or more.

Next, in step S4, the photoresist layer is removed.

Thereafter, in step S5, another photoresist layer is formed on thelayered structures of the first UBM layer 50 and the second UBM layer 51by spin coating.

Then, the photoresist layer is exposed to light, developed, and hardenedso as to form openings in the photoresist layer at positions where theexternal connection protruding electrodes are to be formed.

Next, in step S6, the underlayer 52A and the low-melting metal layer 52Bof the external connection protruding electrodes 52 are successivelyformed in the openings of the photoresist layer. At this point, part ofthe low-melting metal layer 52B extends on the photoresist layer.

Thereafter, in step S7, the photoresist layer is removed.

Next, in step S8, unnecessary portions of the first UBM layer 50 areremoved by so-called wet etching using the second UBM layer 51 as amask.

Next, in step S9, the low-melting metal layer 52B is caused to melt byreflow heating so as to be shaped into substantial spheres. As a result,the substantially spherical external connection protruding electrodes 52are formed on the layered structures of the first UBM layer 50 and thesecond UBM layer 51 over the semiconductor substrate 41.

After the semiconductor device 100 where the substantially sphericalexternal connection protruding electrodes 52 are thus formed isflip-chip mounted (mounted face-down) on the wiring board 71, theexternal connection protruding electrodes 52 and additional solder(solder precoat, not graphically illustrated) provided on the electrodepads 72 of the wiring board 71 are caused to melt by reflow heating soas to connect the external connection protruding electrodes 52 of thesemiconductor device 100 and the electrode pads 72 on the wiring board71.

Next, the space between the semiconductor device 100 and the wiringboard 71 is filled with the underfill material 74 (FIG. 7), which isthen hardened.

Thereafter, solder balls are provided on the lower surface of the wiringboard 71, and are subjected to reflow heating and cooling, so that theexternal connection protruding electrodes 75 are provided on the lowersurface of the wiring board 71.

If desirable, a resin sealing part that covers the semiconductor device100 may be provided before providing the external connection protrudingelectrodes 75.

As a result, the semiconductor device 200 according to the firstembodiment is formed.

Semiconductor Device Manufacturing Method According to Second Embodiment

The semiconductor device (element) 150 illustrated in FIGS. 10A and 10Baccording to the second embodiment may be formed through the followingprocess.

The inorganic insulating layer 48 and the organic insulating layer 49are successively deposited and formed by a known method on themulti-layer interconnection layer 43 provided over the semiconductorsubstrate 41. At this point, openings for selectively exposing thesurfaces of the electrode pads 47 are selectively formed in theinorganic insulating layer 48 and the organic insulating layer 49.

That is, selective etching is performed on the inorganic insulatinglayer 48 covering the electrode pads 47 so as to form openings in theinorganic insulating layer 48, the openings exposing the surfaces of thecorresponding electrode pads 47 in multiple regions.

Next, the organic insulating layer 49 is deposited on the inorganicinsulating layer 48. Selective etching is performed on the organicinsulating layer 49 as well so as to form openings corresponding to theopenings provided in the inorganic insulating layer 48 on the electrodepads 47. As a result, the upper surfaces of the electrode pads 47 areexposed in the respective openings provided in the organic insulatinglayer 49.

Next, the lower layer (a metal layer formed of the same material as thefirst UBM layer 50 in the first embodiment) of the UBM layer 57 isformed on the exposed portions of the electrode pads 47 and the organicinsulating layer 49 by sputtering.

Next, the intermediate layer (a metal layer formed of the same materialas the second UBM layer 51 in the first embodiment) of the UBM layer 57is deposited on the lower layer of the UBM layer 57 by so-calledselective plating using a photoresist layer as a mask.

Further, a photoresist layer is applied and formed on the intermediatelayer of the UBM layer 57 by spin coating. The photoresist layer isexposed to light, developed, and hardened so as to form openings in thephotoresist layer which openings correspond to where the externalconnection protruding electrodes 52 are to be formed over the electrodepads 47.

Then, the upper layer (a metal layer formed of the same material as theunderlayer 52A of the external connection protruding electrodes 52 inthe first embodiment) of the UBM layer 57 is formed in the openings ofthe photoresist layer by electroplating.

Next, the low-melting metal layer (external connection protrudingelectrode layer) 52B is formed on the upper layer of the UBM layer 57 inthe openings of the photoresist layer by electroplating. The low-meltingmetal layer is formed so that part of the low-melting metal layerextends on the photoresist layer.

Thereafter, the photoresist layer is separated and removed, andunnecessary portions of the UBM layer 57 are removed by so-called wetetching using the external connection protruding electrode layer 52B asa mask.

As a result, in each electrode pad part, the UBM layer 57 is provided incontact with the surface of the electrode pad 47 in the correspondingopening of the organic insulating layer 49 and to extend on the organicinsulating layer 49 around the electrode pad 47.

Next, the external connection protruding electrode layer 52B is causedto melt by reflow heating to be shaped into substantial spheres. As aresult, the substantially spherical external connection protrudingelectrodes 52 are formed on the UBM layer 57.

After the semiconductor device 150 where the substantially sphericalexternal connection protruding electrodes 52 are thus formed isflip-chip mounted (mounted face-down) on the wiring board (FIG. 7), theexternal connection protruding electrodes 52 and additional solder(solder precoat, not graphically illustrated) provided on the electrodepads 72 of the wiring board 71 are caused to melt by reflow heating soas to connect the external connection protruding electrodes 52 of thesemiconductor device 150 and the electrode pads 72 on the wiring board71.

Next, the space between the semiconductor device 150 and the wiringboard 71 is filled with the underfill material 74 (FIG. 7), which isthen hardened.

Thereafter, solder balls are provided on the lower surface of the wiringboard 71, and are subjected to reflow heating and cooling, so that theexternal connection protruding electrodes 75 are provided on the lowersurface of the wiring board 71. If desirable, a resin sealing part thatcovers the semiconductor device 150 may be provided before providing theexternal connection protruding electrodes 75.

As a result, a semiconductor device according to the second embodimentis formed.

According to an aspect of the present invention, one or more of theabove-described features may be applied to semiconductor devicesincluding those to be mounted on a wiring board through externalconnection protruding electrodes.

All examples and conditional language recited herein are intended forpedagogical purposes to aid the reader in understanding the inventionand the concepts contributed by the inventors to furthering the art, andare to be construed as being without limitation to such specificallyrecited examples and conditions, nor does the organization of suchexamples in the specification relate to a showing of the superiority orinferiority of the invention. Although the embodiments of the presentinventions have been described in detail, it should be understood thatvarious changes, substitutions, and alterations could be made heretowithout departing from the spirit and scope of the invention.

1. A semiconductor device, comprising: a plurality of electrode padsprovided in an interconnection layer over a semiconductor substrate; aninsulating layer provided on the interconnection layer so as to exposeportions of the electrode pads; a plurality of conductive layers havingrespective first ends thereof connected to the exposed portions of thecorresponding electrode pads so as to extend therefrom on the insulatinglayer; and a plurality of protruding electrodes provided at respectivesecond ends of the conductive layers, wherein the conductive layersextend in a given direction relative to the electrode pads.
 2. Thesemiconductor device as claimed in claim 1, wherein the electrode padsare provided at substantially equal intervals vertically andhorizontally in a matrix on a principal surface of the semiconductorsubstrate.
 3. The semiconductor device as claimed in claim 2, whereinthe protruding electrodes are provided at substantially equal intervalsvertically and horizontally in a matrix on a principal surface of thesemiconductor substrate.
 4. The semiconductor device as claimed in claim1, wherein distances between the electrode pads and the correspondingprotruding electrodes connected to the electrode pads through theconductive layers are equal.
 5. The semiconductor device as claimed inclaim 1, wherein the conductive layers extend in a uniform direction. 6.The semiconductor device as claimed in claim 1, wherein the conductivelayers extend in a direction from a center of the semiconductorsubstrate toward a periphery thereof.
 7. The semiconductor device asclaimed in claim 1, wherein the conductive layers extend in a directionfrom a periphery of the semiconductor substrate toward a center thereof.8. The semiconductor device as claimed in claim 1, wherein theinsulating layer comprises: an inorganic insulating film; and an organicinsulating film formed on the inorganic insulating film.
 9. Thesemiconductor device as claimed in claim 8, wherein the inorganicinsulating film has openings on the electrode pads, the openings beinggreater than or equal to 15 μm in diameter.
 10. The semiconductor deviceas claimed in claim 9, wherein the organic insulating film has openingsformed in the openings of the inorganic insulating film.
 11. Thesemiconductor device as claimed in claim 8, wherein the organicinsulating film is more than or equal to 5 μm in thickness.
 12. Thesemiconductor device as claimed in claim 1, wherein the conductivelayers comprise a plurality of metal layers.
 13. The semiconductordevice as claimed in claim 12, wherein the conductive layers comprise: afirst under-bump metallization layer formed of a material including oneof titanium and chromium; and a second under-bump metallization layerformed of a material including one of copper and nickel.
 14. Thesemiconductor device as claimed in claim 1, wherein the interconnectionlayer comprises an interlayer insulating film having a relativedielectric constant lower than or equal to
 5. 15. The semiconductordevice as claimed in claim 1, wherein the protruding electrodes have oneof a substantially hemispherical shape and a substantially cylindricalshape.